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Geats_X's avatar
Geats_X
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1 year ago

problem to use F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*

Hi, I want to use F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* to generate a demo with gen3 1x4 mode. When I was compiling, the following error occurred: Error(22728): Synthesis is run ...
Pcie
Geats_X's avatar
Geats_X
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1 year ago

But in the design of Gen3 1x16, the PIO module only supports 256 bit or 512 bit, while the bit width of Gen3 1x4 is 128 bit. I don't know how to use it when it's 128 bit.

RongY_altera's avatar
RongY_altera
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1 year ago

The 128/256/512 bit means the data width for user logic.

Regards,

Rong

  • Geats_X's avatar
    Geats_X
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    1 year ago

    So if I use the pio example design of gen3 1x16, I need to replace pio0 and mem0 modules with my own user logic. This will result in the error I explained, won't it? What I want to know is what user logic should include or at least include, so that those errors will not occur during compilation.