MCDMA/PCIe - what is frequency of coreclkout_hip?

Hello,

In the user guide, with H-tile types - Gen3x8, application clock or coreclkout_hip frequency = 250 MHz. But I could not verify it in the TA clock report.

Instead, I could see

"dut|dut|hip|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0"

and its frequency is 500 MHz.

It matches the constraints below:

set clk_source_freq "250.0 MHz"
set datarate_100m  80
...
# 500M for  aibx2 clocks if BW less or equal 64G
} elseif { [expr $datarate_100m * 8] <= 640 }  {
  dict set multiply_factor_dict aib_internal_div 2
  dict set divide_factor_dict   aib_internal_div 1
  dict set multiply_factor_dict clkout 1
  dict set divide_factor_dict   clkout 1
}
...

create_generated_clock \
              -name  $inst|xcvr_hip_native|ch${channels} \
              -source $no_inst_tx_internal_div_reg \
              -master_clock $tx_internal_div_reg_name \
              -multiply_by [dict get $multiply_factor_dict clkout] \
              -divide_by   [dict get $divide_factor_dict   clkout] \
              $no_inst_tx_clkout -add

I think this clock is transport-layer clock and it is used to derive application clock/ coreclkout_hip / pld_clk250 as in the code below

assign  coreclkout_hip = enable_512adapter_hwtcl? pld_clk250                : coreclkout_hip_wire    ;
...

altera_ep_g3x16_avst512_io_pll_s10 altera_avst512_iopll (
		.outclk_0      (pld_clk250),
		.refclk        (coreclkout_hip_wire),
		.rst           (~pin_perst),
        .locked        (iopll_locked),
        .permit_cal    (serdes_pll_locked_wire)
	);

Do I understand it correctly?

If it is correct, then, it is confusing to me. Here is what I found.

I use application clock / coreclkout_hip as the refclk of PLL to derive another clock domain (200 MHz). The setting of PLL is

• Reference clock = 250 MHz
• Output clock = 200 MHz

However, when re-check the TA clock report:

• Reference clock = 500 MHz
• Output clock = 400 MHz

what is wrong here?

My platform is Stratix 10 MX | Quartus Prime Pro ver 22.2

Thank you,

TN