Wincent_Altera
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Re: VVP vs VIP Performance
Hi JLee25 For the fmax detail between grade 5 and grade 6 , you may refer to our device datasheet https://docs.altera.com/r/docs/683828/current/intel-cyclone-10-gx-device-datasheet/intel-cyclone-10-gx-device-datasheet?contentId=EP31Bak3TZHiyvdju2DWUg https://docs.altera.com/r/docs/683485/current/cyclone-10-gx-device-overview/cyclone-10-gx-device-overview Hope that clarified, Regards, Wincent17Views1like0CommentsRe: VVP vs VIP Performance
Hi JLee25 , We do not have an official release datasheet to differentiate between both of VVP vs VIP. But I can lay down some of the suggestion based on my understanding/experience , hope that could help you to be more clear as what you need to choose for your project. In common way, VIP = smaller & simpler for low-performance designs, while VVP = significantly more efficient when performance scales up. VIP is a legacy video processing architecture that is simpler and uses fewer resources for low-resolution, single-stream designs, but it typically supports only 1 pixel per clock and does not scale well for high resolutions like 4K. VVP is a newer, more advanced architecture that supports multiple pixels per clock, making it much better for high-resolution, high-frame-rate, and multi-stream applications. While it may use slightly more logic and introduce higher latency, it provides better overall efficiency, especially in complex pipelines, with improved DSP and memory usage. In summary, VIP is suitable for simple and existing designs, while VVP offers better scalability, performance, and long-term support for modern video systems. Hope that clarified, Next I will suggest to talk with any Altera's FAE or your Local Altera's Distributor for the product recommendation (I believe they can have a better review on your project requirement and provide the best product/IP that fit well with your project. Let me know if there is anything else you think I can better assist you. Regards, Wincent_Altera9Views0likes0CommentsRe: R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hi Jayden , should we keep both txdatavalid_0 and txdatavalid_1 asserted to 1, and drive TS1 Ordered Sets on txdata[9:0] during the reset release sequence? >> Do not hold txdatavalid_0/txdatavalid_1 high and do not drive TS1/TS2 during the reset‑release sequence. >> While txelecidle_i is asserted, the PHY remains in Electrical Idle and ignores txdata/txdatavalid. TS1/TS2 placed on txdata would not be transmitted. reset‑release timing (Figure 49) shows Electrical Idle held and labels TX data as “NA” until reset is complete and the lane is in P0/Gen1. >> During reset‑release if refer to the figure, it keep the transmitter in Electrical Idle (txelecidle_i asserted for all active lanes, e.g., 0xF for x4) and treat txdatavalid_0/txdatavalid_1 as deasserted/don’t‑care. The PHY ignores TX data while in Electrical Idle. >> Switch to the normal PIPE Direct TX datapath behavior (your Figure 48) only after the PIPE Direct reset sequence is complete and the lane is in P0 at Gen1 and ready. At that point, exit Electrical Idle and begin link training; when you start sending TS1/TS2, drive txdata[9:0] with the ordered sets and strobe txdatavalid_0/txdatavalid_1 per the Gen1 valid‑data pattern shown in the TX datapath figure. Is this an abnormal condition? Or is it expected behavior, and the Figure 49 timing diagram is only showing a conceptual relationship rather than a strict timing dependency? >> The table is something we tested internally and proven 99.9 % of the function is working well in such situation. >> Hence, I would suggest you to follow it, except there is a special requirement on your project (who blocking you from following it). >> from your waveform, the cdrlock2data start to be high before the phystatus is asserted. do you do the transition of powerdown from P1 to P0 ? or all the way it is P0 ? If I provide the .sof file, the .stp file, and a simple guide mentioning a set of sticky/debug signals that make the behavior easy to observe, would it be possible for you to run the same validation on your board and check whether the same issue is reproduced? >> I would suggest you to check directly with the Distributor's FAE on this request. Regards, Wincent_Altera14Views0likes0CommentsRe: Verifying R-Tile PIPE Direct x8 lane-to-pin mapping on Agilex 7 I-Series Dev Kit
Hi Dexter22 , For the Pin-out Guide , you may refer to Agilex 7 Device Family Pin Connection Guidelines Refclk connection for Octet 0 , you may check under section 2.2.1. Clocking https://docs.altera.com/r/docs/683501/25.1.1/r-tile-avalon-streaming-ip-for-pci-express-user-guide/clocking?tocId=gEL4qX1L4Lucx8mOu~Rukg let me know if there is anything unclear. Regards, Wincent_Altera13Views0likes0Comments