User Profile
Wincent_Altera
Regular ContributorJoined 5 years ago
User Widgets
Contributions
Re: PCIe Simulation using Quartus Pro 25.1.1
Hi amolkumar , From the fail scenario, I will assume that will be compatible problem between your simulator version --> Quartus version Since Quartus v26.1 working well , I would suggest you to go with v26.1 directly Regards, Wincent_Altera35Views0likes3CommentsRe: VVP Protocol Converter Not work
Hi JLee25 , Based on what you provided, most likely remaining cause is that the MM writes are not reaching the compiled Protocol Converter instance correctly— for example, wrong base address/offset, incorrect byte addressing, or an inactive control-interface clock/reset domain. Can you please check from there ? Regards, Wincent_Altera10Views0likes0CommentsRe: Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs
Hi Dexter22 , Some of your question, you may get the answer from PCI specification. But I can try my best understanding to help you answer, hope that can be a good reference point for you. 1. IF refer to PCI Express Base Specification Revision 6.2, Section 2.9.2, “Transaction Layer Behavior in DL_Up Status”. The guide mentioned : “When transitioning from a non-DL_Up status to a DL_Up status and the Auto Slot Power Limit Disable bit is Clear in the Slot Control Register, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Slot Power Limit Value fields of the Slot Capabilities Register.” Hence I would said the spec ties this message to the DL_Up transition, not to completion of Configuration Reads, so seeing Set_Slot_Power_Limit before the first CfgRd0 is normal. 2. IF refer to PCI Express Base Specification Rev. 4.0 Version 1.0, Section 2.2.8, “Message Request Rules”. “Message Requests are posted and do not require Completion.” “The component on the other side of the Link (with Endpoint, Switch, or Bridge Functions) that receives Set_Slot_Power_Limit Message must copy the values in the data payload into the Device Capabilities register associated with the component's Upstream Port.” So your endpoint should not send Cpl/CplD for this message. The required behavior is normal DLL reliability handling plus, functionally, capturing the payload into the appropriate slot-power-limit fields if your implementation exposes that capability behavior. 3. I never try such customization before, but ideally it shall be yes , because PCIe DLL reliability depends on valid ACK/NAK, sequence tracking, replay buffering, and timeout/replay behavior; if ACKs are unusable, forward progress can stall and link recovery behavior can follow. 4. If refer to R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express User Guide, Section 2.4, “PIPE Direct Mode”. “When implementing a Soft IP Controller using the R-tile IP for PCI Express in PIPE Direct mode, the FPGA device must be fully configured in order to start the link training sequence since the Controller is in the FPGA fabric” “The soft IP controller must release the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signal out of reset after the per-lane lnX_pipe_direct_tx_transfer_en_o signal is asserted.” “There is only one PERST# pin ( pin_perst_n) on the R-tile. Therefore, toggling pin_perst_n will affect the entire R-tile. This pin also resets the EMIB interface.” 5. Since you already capture LTSSM, DLL, replay, LCRC, and raw PIPE data, the most useful additional captures are the tx_transfer_en_o to lane-reset relationship, unused-lane powerdown_i handling, and PERST# / EMIB / refclk sequencing, because those are the guide-called-out controls most likely to block clean bring-up before Config traffic ever becomes stable. 6. based on my understanding , due to PCIe flow control is separate by traffic type and separate for header/data, so a bad Completion-credit advertisement can block progress even though the InitFC1/2 exchange itself finished. But that is just my assumption based on my own experience, please treat that as reference purpose. 7. You may refer to below chart, those are proven sequence of Pin Perst , timing of other signal to be work well for PIPE direct mode https://docs.altera.com/r/docs/683501/26.1/r-tile-avalon-streaming-ip-for-pci-express-user-guide/pipe-direct-reset-sequence https://docs.altera.com/r/docs/683501/26.1/r-tile-avalon-streaming-ip-for-pci-express-user-guide/pipe-direct-speed-change Regards, Wincent_Altera1View0likes0CommentsRe: Cyclone IV GX PCIe Hard IP behaves differently on Intel Core I7 vs Xeon root complexes
Hi SharmaUmesh278 , Thanks for your response, you are most welcome, do file a new thread whenever you need any help. We will be there for you. Looking forward to see you again in the future. Regards, Wincent_Altera10Views0likes0CommentsRe: VVP Protocol Converter Not work
Hi JLee25 , Is this from our example design, sorry to said I never try out such customization before. But I can advise based on my own experience for your reference, feel free to point out if my understanding is wrong. Yes, the UG does mention how Lite mode must be programmed, and based on that I do not think video data alone is sufficient here. For the Pixels in Parallel Converter, 4→2 and 2→4 are supported. The UG says it supports any conversion from 1 to 8 pixels in parallel. However, it also says the IP must know how many pixels are in each video line. In Full mode, it gets that from the image information packet in the stream. In Lite mode, the stream has no image information, so you must provide the line information through the register map / control agent interface. For the Protocol Converter in Lite to Avalon mode, the UG says you must program the incoming width through the register map so the IP can determine valid pixels on the last beat of each line, and it also uses width, height, and interlace from the register map to generate the Avalon-ST control packet. The documented Lite-mode registers are IMG_INFO_WIDTH (0x0120), IMG_INFO_HEIGHT (0x0124), IMG_INFO_INTERLACE (0x0128), IMG_INFO_COLORSPACE (0x0130), IMG_INFO_SUBSAMPLING (0x0134), IMG_INFO_COSITING (0x0138), and CTRL (0x0154) to start the IP. So for Lite mode, the UG indicates this is not just “send video data and it should run”; the frame/image information must also be programmed correctly. Regarding register address 75 / vvpBpsCode, I do not see that name in the documented Protocol Converter register map in the UG section for this IP. Based on the published register table, I would avoid depending on it unless there is another official source that documents it. For the Chroma Resampler, if Lite mode is enabled, the UG says the memory-mapped control interface is required. In Lite mode, you need to set at least IMG_INFO_WIDTH (0x0120), IMG_INFO_HEIGHT (0x0124), and IMG_INFO_SUBSAMPLING (0x0134). For your 4:2:2 → 4:4:4 CRS case, I would also check that the instance was built with 4:4:4 output support enabled, and that the runtime OUTPUT_MODE is set to 3 = 4:4:4 if you are controlling it via registers. At this point, based on the UG, my main suspicion is not that 4→2 / 2→4 is unsupported, but that the downstream VVP IPs are not receiving the frame/image metadata they need to begin processing in Lite mode, or valid image information packets in Full mode. Regards, Wincent_Altera6Views0likes0CommentsRe: mipi csi2 tx, upper limit of video width
Hi yumada -san, Sorry for taking some time to get back to you. We were able to reproduce the behavior and found that it is related to the line buffer depth in the CSI-2 Tx IP. For the configurations you mentioned, the configured buffer is not large enough to hold a complete line of data with sufficient margin. In this situation, the transmitter can stall before the first packet is produced. As a general guideline, the line buffer should be sized to at least two lines where possible, especially for wider image formats such as RAW12 and RGB888, which require more buffer space. This limitation has been addressed in a newer release of Quartus v26.1.1 that supports larger buffer configurations. Once the update done , the issue should be resolved. Let me know if you have any other concern, thanks for pointing this out. Regards, Wincent_Altera23Views0likes2Comments