Wincent_Altera
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Re: HDMI example design errors with Agilex 7
Hi dncmrc1 , May I know which quartus version that you are trying ? I lay down some of the suggestion in order to help you to move a step forward. 1. Create a project targeted the device OPN that you need, for example, in this case, you need to select your targeted devkit 2. Select HDMI from the IP Catalog 3. On the Target Development Kit "Select Board" option, choose "Customer Development Kit" and click on Generate Example Design After generation finishes, open the QSF file, there are some of the set_location_assignments with "Your_location" that needs to be updated. You can refer to the the design example (since the devkits are the same) and copy over the setting: (FOR YOUR REFERNCE PURPOSE ONLY) The error you seeing might due to clock and pin type mis-matching Do carefully checking each pin carefully https://www.altera.com/design/devices/resources/pinouts#tab-blade-1-3 Regards, WincentRe: MCDMA IP D2H Queue Reset Failure during Channel Re-allocation
Hi Ashoo , Based on my understanding.. Question 1 - The behavior where Channel 2 gets stuck when Channel 1 is active, but resumes once Channel 1 stops, is classic evidence of resource contention or starvation. This typically happens at the memory bus (AVMM) or descriptor fetch interface, where one channel monopolizes shared hardware resources, preventing others from proceeding. Question 2 - MCDMA typically using round-robin for channel access. This can depend on your IP configuration, but in most cases, the arbitration policy is not designed for strict fairness or bandwidth balancing. Question 3 - As more channels are initialized, each new queue reset takes longer. This is likely due to the reset logic waiting for access to shared hardware (e.g., AVMM, state machines, FIFOs). These delays are aggravated when other channels are active and holding bus resources. Hope that able to help you to move forward. I am just trying to share some experience based on what I understand from your issue, do correct me if there is anything I misunderstand. Regards, WincentRe: MCDMA IP D2H Queue Reset Failure during Channel Re-allocation
Hi Ashoo , Glad to hear that you are able to bypass the error, thanks for sharing with me how you work on it. Based on my understanding. reasons for its presence - Without a timeout, if the queue reset bit never deasserts (for example, due to hardware malfunction or misconfiguration), the process would get stuck in an infinite loop. The timeout allows the software to detect hardware problems and handle them gracefully (log, clean up, alert the user, etc.). Why 2048 Microseconds - The value (2048 µs) is likely chosen based on typical hardware reset response times, with a margin for variability. Most hardware queue or register resets are expected to complete in a few microseconds to low milliseconds. If you comment out the timeout - that could potentially cause the hardware or logic ever fails to deassert the reset bit, your code will hang forever at that point, leading to a stuck process or system. I recommend you to consider to increase the timeout value that suit with you system , for example 10000us or more. Regards, WincentRe: R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hi Jayden , Regarding question for Figure 48 vs Figure 49. if user need to perform reset-sequence , they shall follow figure49. While figure48 is common practice for reference purpose only. The reset release sequence diagram is primarily intended for the reset release relationship between the various signals For the actual data handling, the user should refer to the PIPE Direct TX Datapath and PIPE Direct RX Datapath figures. On the TX side, the tx_clkout is always at 500MHz. Depending on which speed you are in, the valid data on the TX path varies between Gen1 to Gen5 and needs to toggle accordingly On the RX path, the rx_clkout varies as per gen, so every clock cycle there is valid data between _0 and _1 signals Hope this clarified. Regards, WincentRe: PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?
Hi Abhi_Krishnan_R , Under page 59 of your provided guide (in the forum description) Got mentioning the way to handle the delay of SOP and EOP by given TLP The maximum latency will be 1/2 clock. Hope this able to help you to move forward. Let me know if I understand this incorrect. Regards, WincentRe: PIPE Direct Reset Release Sequence
Hi Jayden , Question 1, I am recommended to release lnX_pipe_direct_pld_pcs_rst_n_i (Step 4) in the domain of ln0_pipe_direct_pld_tx_clk_out_o, or at least synchronously to it. This ensures the reset release and subsequent logic initialization are properly aligned with the TX clock domain, avoiding metastability and timing issues. While you can use another clock with CDC (clock domain crossing) synchronizers, doing so adds complexity and risk. If you must use a different clock, you must guarantee that the de-assertion is properly synchronized into the TX clock domain, typically with a multi-flop synchronizer. Question 2, Increase your SignalTap pre-trigger buffer to capture events before and after your trigger, so you can see the full sequence. Question 3, I have work with few other customer before, and they are able to bring up the phystatus and cdrlock2data. IF this happen, I would suggest you to check back your logic carefully. few of the common mistake will be make sure lnX_pipe_direct_powerdown_i follows the correct state transitions (P1 → P0 as per PIPE). Double-check reset release timing: Ensure lnX_pipe_direct_pld_pcs_rst_n_i is released after lnX_pipe_direct_tx_transfer_en_o and the TX clock is valid. It is quite hard to narrow down in one single reply, But I hope I am able to provide the best tips for you to narrow the issue quicky. This guide is helpful for your logic designing, perhaps you can refer https://www.intel.com/content/www/us/en/io/pci-express/phy-interface-pci-express-sata-usb30-architectures-3-1.html However, for PIPE Direct mode, there are no example design available, so at the moment I do not have a way to validate this behavior with RTL simulation. If anyone has experience debugging Figure 50 on real hardware, I would appreciate guidance. >> We do have technical Partner that is fully validate this in real HW design. >> IF you need a turnkey solution do consult your local Altera Distributor/sales to get the partner name. >> or else, me and the community contributor will continue to ensure your success via this forum platform. Regards, Wincent
