Wincent_Altera
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Re: System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi SYiwe , If you are using .sof file, you may need to perform host reboot to get the PCIe link enumerate. I had created before an document for PCIe Getting Started , you may refer the document in link below Although it is for Agilex 7, but the overall step shall be the identify. https://community.altera.com/discussions/ip-and-transceiver/how-to-run-pcie-gen-5-design-example-using-altera-fpga-device/125814 In the signal tap, ltssm stucks at 0, and p0_pin_perst_n is 0 too. >> Can you show me the signal ? A printscreen will do. Regards, WincentRe: System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi SYiwe , Which device that you are using ? Agilex 5 Modular devkit ? IF yes, I would suggest to try out the design example from IP Catalog. A signal tap is instanced and I found the system PLL cannot be locked with signal tap, >> Do you capturing the ltssm signal ? >> What is the ltssm status ? At the meantime, you may try out the suggestion provided by our community expert FVM as mentioned above Regards, Wincent_AlteraRe: System PLL of Agliex5 PCIE example design cannot be locked after configuration
Hi SYiwe , 1、Is it valid for System PLL to have its reference clock driven from PCIE card edge？According to 4.1.1 of GTS AXI Streaming IP for PCI Express* User Guide: Agilex 5 and Agilex 3 FPGAs and SoCs (ug813754), reference clock for System PLL should from a independent and free-running local clock source. >> Yes, it shall be independent and free running 2、If the answer of above question is positve, how should I debug to make the System PLL work? >> did you compile the design ? is it running full compilation without any issue ? >> IF yes, please tap a signaltap , or you may use lspci to check either the ltssm is able to link up or not/ >> Next, which design that you are using ? is this custom design or from our design example - I suggest to try direct the design example from Quartus IP catalog Sorry for late reply due to Lunar New Year holiday, Happy New year to you as well. Looking forward to hear back from you. Regards, WincentChiah_AlteraRe: Agilex-7 MSI-X missing om AXI MCDMA for PCIe
Hi Mikhail_a , I lay down some document, Hope it can help you to move forward 5.4.8. User Event MSI-X Interface https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/user-event-msi-x-user_msix 9. Registers https://docs.altera.com/r/docs/683821/25.3.1/multi-channel-dma-ip-for-pci-express-user-guide/registers https://docs.altera.com/r/docs/683821/25.3.1/multi-channel-dma-ip-for-pci-express-user-guide/control-registers The address range for the MSI-X Table and PBA is within the configuration, control and status registers: 0x10_0000 – 0x1F_FFFF I'm still interested if I need to enable MCDMA somehow so it can handle MSI-X requests. Because from MCDMA control registers description it is not that obvious if we need to do something for MSI-X to be sent. >> If you configure the IP core to have 1 DMA channel, the table has 4 entries, where each entry is 4 DWORDs, 1 entry for each H2D/D2H DMA/User Event vector. >> I actually think this is somewhat best explained in our MACsec System Design User Guide - our MACsec IP utilizes the MCDMA IP, but needs to send its own MSI-X interrupts using the exact same user interrupts you are trying to use. Please refer to section 2.6. Interrupts https://docs.altera.com/r/docs/767516/23.4/macsec-system-design-user-guide/interrupts Regards, WincentRe: Agilex-7 MSI-X missing om AXI MCDMA for PCIe
Hi Mikhail_a , As I understood from the doc MSI-X messages are written by MCDMA, but should we enable it or initialize if in our case we don't use it at all? >> If I refer to the user guide , the default value is 1. If you dont use it at all perhaps you can set it as zero our pcie endpoint actually sends MSI-X TLP to the root complex? the acual write transaction from the root complex was issued in the host system? >> Based on my understanding on PCIe architecture , the Endpoint generates MSI-X by sending a Memory Write TLP upstream. The Root Complex does not issue that write; it receives it and converts it into a CPU interrupt. What is the design you are using ? is it custom design ? Or design generate purely from our IP catalog ? If this is custom design, I would suggest to generate one from our IP catalog https://docs.altera.com/r/docs/847470/25.1.1/gts-axi-multichannel-dma-ip-for-pci-express-user-guide/bam-bas-mcdma-mode Regards, WincentRe: Agilex 7 R-Tile PIPE Direct Mode: Raw Rx Data Misalignment - Is Soft Word Alignment Needed?
Hi Dexter22 , Based on the your provided result Yes — in PIPE Direct mode on Agilex 7 R‑Tile, the hard IP intentionally bypasses PCS word/symbol alignment. You will see raw, unaligned serialized data on the PIPE RX interface. Yes — you are responsible for soft word alignment (comma/K28.5 detection with bitslip), bit orientation handling (bit‑reversal if needed), and subsequent 8b/10b or 128b/130b processing in the FPGA fabric. No — there is no IP parameter to turn on hard PCS alignment while retaining PIPE Direct. If you want hard alignment and decoding, you must use the standard PCIe controller modes (not PIPE Direct). As PIPE Direct Mode is mostly customize by user (no available design example provided by Altera), I would lay down some of debug suggestion based on my experience, hope that can help you to move a step forward. Verify bit ordering: If your K28.5 only appears after reversing the 10 bits, your lane is likely bit‑reversed relative to your decoder. Make the reversal a parameter so you can flip per lane without re‑synthesis. Implement a robust comma detector: Check for both 0011111010 (RD−) and 1100000101 (RD+) across all bit positions of your capture word. Once aligned, validate with running disparity and known training patterns (TS1/TS2) to confirm stability. Confirm your valid‑bit placement: At Gen1/Gen2 speeds, only certain bits of the RX bus are meaningful per cycle (commonly the 10 LSBs of each half). Treat upper bits as don’t‑care until alignment is achieved. Use training patterns as a sanity check: The repeated 0x155 (D10.2) is expected in TS1 fields. Once aligned, you should cleanly parse TS1/TS2 content and comma locations. Regards, Wincent
