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bibo's avatar
bibo
Icon for New Contributor rankNew Contributor
3 years ago
Solved

MCDMA/PCIe - what is frequency of coreclkout_hip?

Hello, In the user guide, with H-tile types - Gen3x8, application clock or coreclkout_hip frequency = 250 MHz. But I could not verify it in the TA clock report. Instead, I could see "dut|dut|...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,


    I think that indicates the Clock Fmax.
    If you changed the optimization Mode from Balanced to Aggressive Area you can achieve the 500MHz.

    The Fmax specification is based on the fast clock used for serial data.

    The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

    Hope this clarified.

    Regards,

    Wincent_Intel

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


The frequency of coreclkout_hip is for gen3x8 is 250 MHz as per mention in the user guide.

Are you using the design example provided in Quartus ?


Can you check if you enable two clock together ?


Regards,

Wincent_Intel


bibo's avatar
bibo
Icon for New Contributor rankNew Contributor
3 years ago

Hi Wincent,

I used the example design provided in Quartus. Running PIO transfer, gencheck, loopback seem OK.

Then, I want to insert our accelerators to receive data from the HOST, doing computations, and send back results to the HOST.

I want to run these accelerators at a lower frequency (200MHz), so I pulled PLL core which uses coreclkout_hip as the reference clock.

But when re-checking TA clock report, it showed the output clock freq = 400 MHz and refclk = 500 MHz

@Wincent_Altera wrote:

Can you check if you enable two clock together ?

Could you clarify this? I could not see where to enable two clocks when pulling the MCDMA IP Core.

There is only 1 selection regarding frequency: "PCIe gen3 x8 - 250 MHz"

Thanks,

TN

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Can you please provide me the printscreen of the TA report that mentioning 500 MHz ?

    Regards,

    Wincent_Intel

    • bibo's avatar
      bibo
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      Sure! This is the PLL configuration

      And the system view with clock interfaces

      And this is what clock report with the final snapshot

      • clkout of the IOPLL

      • And clock network report

      Regards,

      TN

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi,


        I think that indicates the Clock Fmax.
        If you changed the optimization Mode from Balanced to Aggressive Area you can achieve the 500MHz.

        The Fmax specification is based on the fast clock used for serial data.

        The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

        Hope this clarified.

        Regards,

        Wincent_Intel