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bibo's avatar
bibo
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3 years ago
Solved

MCDMA/PCIe - what is frequency of coreclkout_hip?

Hello, In the user guide, with H-tile types - Gen3x8, application clock or coreclkout_hip frequency = 250 MHz. But I could not verify it in the TA clock report. Instead, I could see "dut|dut|...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,


    I think that indicates the Clock Fmax.
    If you changed the optimization Mode from Balanced to Aggressive Area you can achieve the 500MHz.

    The Fmax specification is based on the fast clock used for serial data.

    The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

    Hope this clarified.

    Regards,

    Wincent_Intel

bibo's avatar
bibo
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

Thanks for your reply!

That is why I was confused.

Under "Clock" report in Timing Analysis, it showed 'output_clk" of PLL is 400 MHz.

Meanwhile, my setting ratio of PLL is 'refclk/output_clk' = 250MHz/ 200MHz

That's why I thought refclk frequency should be: 500 MHz, and it violates the user guide where the frequency should be 250 MHz.

Thanks and Regards,

TN

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Glad that you get your answer.

So do you still have any further questions on this forum case ? Or everything is nice ?

if yes, I shall close this case from my place and leave this thread to the public community.


Regards,

Wincent_Intel

  • bibo's avatar
    bibo
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi,

    Thanks for your reply. Could you please make this case open?

    After @FvM reply, I have checked the actual frequency of PLL output_clk = 400 MHz.

    With the setup ratio 250MHz/200MHz, it expects "coreclkout_hip" should be 500 MHz instead of 250 MHz.

    Therefore, I still need to discuss more to know what I was wrong.

    Thanks and Regards,

    TN

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      the printscreen is not clear, could you please provide again ?
      so that I can confirm the issue ?

      Regards,

      Wincent_Intel

      • bibo's avatar
        bibo
        Icon for New Contributor rankNew Contributor
        3 years ago

        Hi,

        Here is the screenshot of clock report

        The clk_wizard_clk_user is output_clk of PLL.

        And, this is my PLL setting

        Thanks and Regards,

        TN

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Apologize for late reply due to holiday.
      Based on the user guide, the maximum H-tile types - Gen3x8, application clock is 250 MHz.
      I dont understand your statement as "With the setup ratio 250MHz/200MHz, it expects "coreclkout_hip" should be 500 MHz instead of 250 MHz."

      Can you please clarified more on this ?
      by logic when you set it as 250 why it shall get 500 MHz instead of 250Mhz ?

      Regards,

      Wincent_Intel

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi,

        There is some reason the frequency is double.
        I suggest you to check the RTL design and see what is connected to the output.
        I am not an expert in timing issues, As I am supporting PCIe design in most of the time.

        Another suggestion to get better support is open a new case with title and category related to timing.
        So that the correct expert will be assigned to help you.
        Do attach the .qar and timing report for that.

        Regards,

        Wincent_Intel