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bibo's avatar
bibo
Icon for New Contributor rankNew Contributor
3 years ago
Solved

MCDMA/PCIe - what is frequency of coreclkout_hip?

Hello, In the user guide, with H-tile types - Gen3x8, application clock or coreclkout_hip frequency = 250 MHz. But I could not verify it in the TA clock report. Instead, I could see "dut|dut|...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,


    I think that indicates the Clock Fmax.
    If you changed the optimization Mode from Balanced to Aggressive Area you can achieve the 500MHz.

    The Fmax specification is based on the fast clock used for serial data.

    The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

    Hope this clarified.

    Regards,

    Wincent_Intel

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for your understanding. I just close in my support portal.

This thread still remain for public command, I will keep you in post if there is any update related team.


If you have a new question, feel free to open a new thread to get support from Intel experts.

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.


Regards,

Wincent_Intel


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

The input clock frequency of H-Tile MCDMA(intel_pcie_mcdma) is 250 MHz and the IP runs on 250MHz only. Please refer the attached snippet.

The paths shown in the timing report are the QHIP paths and not inside MCDMA.

Time period = 4ns. Clock Frequency(dut.dut.mcdma.clk)= 250 MHz.

  • bibo's avatar
    bibo
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Wincent,

    Sorry for my late reply due to holiday.

    From your attached snippet, one thing can be confirmed is MCDMA clock is 250 MHz.

    Your statement:

    @Wincent_Altera wrote:

    The paths shown in the timing report are the QHIP paths and not inside MCDMA.

    And because the reference clock of PLL is taken from "coreclkout_hip".
    It means the reference clock is QHIP paths and it is not 250 MHz, isn't it?

    Regards,

    TN

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,


      My answer should be yes for your question.

      Regards,

      Wincent_Intel

      • bibo's avatar
        bibo
        Icon for New Contributor rankNew Contributor
        3 years ago

        Hi,

        Thanks for your confirmation.

        That clears my doubt.

        That means '''coreclkout_hip' is not 250MHz as specified in the user guide.

        Regards,

        TN