I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi WQIUS,

Thanks for your update on the details on changes. For your information, the reason of the previous unfit is because you have assigned the XCVR channels to the physical channel 1 of the GXB bank. In the selected part of yours, there is only 3 XCVR channels. Only physical channel 1 have the CMU PLL which can drive duplex XCVR. Therefore, you can only place your duplex XCVR channel to physical channel 0 or 2 so that you can have CMU PLL to provide high speed clock to your TX channels.

Please let me know if there is any concern. Thank you.

Chee Pin

​Hi,

Yes, you are right. If you want to use the CMU PLL, you are left with only CH0 and 2 to use. If you want to use all the CH0, 1 and 2, you may explore into using external fPLL. You can use one fPLL to drive all the 3 CHs at the same data rate. If you are planning to use two fPLLs to support different data rate, you might need to create some simple test design to try out to see if it works as I am not sure if there is enough fPLL to drive the XCVR banks on the same side.

You may refer to the wiki design example on how to use external fPLL:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example

Hi,

Yes, your understanding is correctly. If you would like to CMU PLL, then you can only use CH0 and CH2. If you plan to use 3 of the duplex XCVR channels at the same data rate, then you can explore using external fPLL to drive all the 3 XCVR channels. Note that when you use the CH1 as duplex XCVR, then you would not have a CMU PLL because it is located in the RX channel.

You may refer to the following design example for further details:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example

Note that in your selected part, there is only one 3-CH XCVR banks. If you would like to implement 2 different data rates, I am not sure if there are sufficient fPLL resources on the same side for your selected part, You might need to create test design to check on this.

Please let me know if there is any concern. Thank you.

Chee Pin

Hi,

Regarding your inquiries on setting the serial loopback in Custom PHY, for your information, you will need to perform register writing to enable the serial loopback. You may refer to the XCVR PHY IP user guide -> "PMA Control and Status Registers" -> "phy_serial_loopback" register for further details.

By the way, to ease your debugging, I would recommend you to create a new simple one channel test design with Custom PHY in RTL to avoid any dependency on the XCVR toolkit and design example.

You may try to refer to the following AV Custom PHY design to enable serial loopback:

https://fpgawiki.intel.com/wiki/Arria_V_Transceiver_PHY_Basic_Design_Examples#Arria_V_Custom_PHY_simple_ways_to_enable_internal_serial_loopback_design_examples

Please let me know if there is any concern. Thank you.

Chee Pin