I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi： Now, I have a new question to ask you. In the file”AN585 page:3:PHY LOOPBACK ”, it mentioned the message to enable the loopback function in GXB: To set the sd_loopback bit , you need to do a configuration write to the PCS control register. Also, I learn that the custom PHY can set loopback function, if there is a detailed steps to follow to set the loopback function? And, I download the design examples “transceiver_toolkit_13_0sp1_qar”,in which there is a folder “cv_GX_1ch_40b_3125mbps”,I change it to 1000Mbps, and change the device, but when I run the transceiver toolkit, it always has some error, then, I delete the PLL in the top.v file ,and there is no error . As I do not set the loopback, I can only see the TX . So, what is this problem? And ,How can I set if I want to check the TX and the RX channel with loopback? (cyclone V： 5CGXFC3B7F23C8N) Thank you. —————————————————————— 王秋实 中广核研究院北京分院 技术支持部 联系电话：010-82193500-279 手机 ：18810644922 邮箱 ：wangqiushi@cgnpc.com.cn