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WQIUS's avatar
WQIUS
Icon for New Contributor rankNew Contributor
7 years ago

I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

I download the design example “cv_GX_1ch_40b_3125mbps”，change the chip to mine（ 5CGXFC3B7F23C8N），the Channel 1 has error，how can I do？
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

​Hi,

Yes, you are right. If you want to use the CMU PLL, you are left with only CH0 and 2 to use. If you want to use all the CH0, 1 and 2, you may explore into using external fPLL. You can use one fPLL to drive all the 3 CHs at the same data rate. If you are planning to use two fPLLs to support different data rate, you might need to create some simple test design to try out to see if it works as I am not sure if there is enough fPLL to drive the XCVR banks on the same side.

You may refer to the wiki design example on how to use external fPLL:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example