I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi: thank you for your reply. According to your point of view, only channels 0 and 2 can use the CMU PLL, which provide a high-speed clock . But if I want to use channel 1 as a channel for fiber-optic communication(SFP), is it not feasible? thank you