I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi,

Regarding your inquiries on setting the serial loopback in Custom PHY, for your information, you will need to perform register writing to enable the serial loopback. You may refer to the XCVR PHY IP user guide -> "PMA Control and Status Registers" -> "phy_serial_loopback" register for further details.

By the way, to ease your debugging, I would recommend you to create a new simple one channel test design with Custom PHY in RTL to avoid any dependency on the XCVR toolkit and design example.

You may try to refer to the following AV Custom PHY design to enable serial loopback:

https://fpgawiki.intel.com/wiki/Arria_V_Transceiver_PHY_Basic_Design_Examples#Arria_V_Custom_PHY_simple_ways_to_enable_internal_serial_loopback_design_examples

Please let me know if there is any concern. Thank you.

Chee Pin