I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi,

Yes, your understanding is correctly. If you would like to CMU PLL, then you can only use CH0 and CH2. If you plan to use 3 of the duplex XCVR channels at the same data rate, then you can explore using external fPLL to drive all the 3 XCVR channels. Note that when you use the CH1 as duplex XCVR, then you would not have a CMU PLL because it is located in the RX channel.

You may refer to the following design example for further details:

https://fpgawiki.intel.com/wiki/Cyclone_V_Transceiver_PHY_Basic_Design_Examples#Cyclone_V_Native_PHY_with_external_fPLL_design_example

Note that in your selected part, there is only one 3-CH XCVR banks. If you would like to implement 2 different data rates, I am not sure if there are sufficient fPLL resources on the same side for your selected part, You might need to create test design to check on this.

Please let me know if there is any concern. Thank you.

Chee Pin