I use the FPGA of cyclone V which type is 5CGXFC3B7F23C8N ,which has 1 GXB Bank （3 transceiver channel）,CH0/CH1/CH2，but CH1 has error

Hi WQIUS,

Thanks for your update on the details on changes. For your information, the reason of the previous unfit is because you have assigned the XCVR channels to the physical channel 1 of the GXB bank. In the selected part of yours, there is only 3 XCVR channels. Only physical channel 1 have the CMU PLL which can drive duplex XCVR. Therefore, you can only place your duplex XCVR channel to physical channel 0 or 2 so that you can have CMU PLL to provide high speed clock to your TX channels.

Please let me know if there is any concern. Thank you.

Chee Pin