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hxhaa's avatar
hxhaa
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3 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output_files directory. The pof file program succeefully, but the host can't find the device 0ddb.

Is there are any tips the DE_UG don't describe?

Cxl
  • WZ2's avatar
    WZ2
    3 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


14 Replies

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thanks for your reply.

      There are some questions need your help.

      What is user mode? How to enter into?

      The default switch setting for DK-DEV-AGI027RBES switch4 is on/off/off/off in user guide, but it makes the JTAG unknown. I try to program flash at off/off/off/off, and use at on/off/off/off, it can't work. How to set it?

      I know it may be caused by the system, but now the D11 LED is off. It means I have some wrong operation for FPGA.

      Maybe a pof is needed if these questions are solved but it also can't work.

      Best regards,

      hxhaa

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi there,

    I see, you may refer the wrong user guide. RBES is the new board, sw4 is a JTAG setting for the old board, and you can refer the default switch on page 13 on https://www.intel.com/content/www/us/en/docs/programmable/683288/current/overview.html

    Pay attention, on sw8.

    And if you still cannot find the device, please go to programmer-> tools-> configuration debugger-> device info and read out the boot stage of device to make sure the device enter into user mode.

    Best regards,

    WZ


    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi WZ,

      I set sw8 off/off/off/off and sw4 off/off/on/off and enter into user mode. Now the D11 of fpga turns on. Is it means the fpga configuration succussed？

      But the system still can't grep 0ddb device, maybe you are right it is caused by the system. I will try it at other system if the fpga work.

      Actually, I refer the 763513/763328 document published at 2023.10.11 for quartus 23.3, are there other documents to use? I want to know more about cxl ip and how to use its example design.

      Best regards,

      hxh

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi there,

    Yes, according to your description, your device's configuration success. Before check the system bug, you check the state of link to make sure the link training succussed. I also will upload a pof file which I verified.


    About documents, 723393 also a useful document, however it seems belong to confidential info, you can ask it to your FAE or sales.

    Best regards,

    WZ


    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi，

      Thanks for your help, I succeed to find the 0ddb in my system and run the mlc.

      Best regards

    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi ,

      I notice the cxl example design with 4 slices can't be generated with specific board. I selected none in example design development board, and assigned pin. I refer the .qsf in example in install package download from Intel Agilex® 7 FPGA I-Series Development Kit, and assign pin for dimm channel. But it can't work.

      Considered about no classic example to use, I guess the use of dimm is different from comp. I notice that the example memory design in install package for dimm is x4 x72, and for comp is x8 x72.

      Are there any qsf or design to refer for using more than 2 slice. I need to use all ddr channels on the board.

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi there,

    Regarding the issue with 4 slices, we are also negotiating with the design team about it. I have run simulations on version 23.3, and the behavior is as expected. However, when it comes to actual board validation, due to some coupling issues with AXI and EMIF and the lack of ideal boards (currently RBES has 2 DDR), the problem has not been resolved smoothly. However, feedback from customers like you can help us continuously improve and expedite the resolution of this issue. I will inform you in the Forum if there are any new developments.

    Best regards,

    WZ

    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi,

      You say RBES has 2 DDR, do you mean that RBES's dimm can't be used as memory for cxl? Is it possible to implement more than 2 slices on RBES?

      Best regards

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    It can be. I'm sorry that my words caused misunderstanding. From my point of view, 4slices cxl controlling 4 particles is what I expect and think is a reasonable application condition.


    • hxhaa's avatar
      hxhaa
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi，

      I implement 2cxlip in top level， but intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/synth/intel_rtile_cxl.sdc said that：

      Refclk and avmm clk only will be created when top level port matches QHIP port. Else no refclk and avmm clk will be created. User need to aware of the port name used. This SDC is for user reference for top level clk creation.
      I modify this file but after synth it will be reset to the start.
      Now there are two refclk0/1/4 for 2 ip, I can't use the same port name as QHIP.Now It can pass the compilation progress and get the sof/pof, and after programmer it did not work. What should I do?
  • xalverti's avatar
    xalverti
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello to all,

    I am trying to program the same FPGA as a Type3 device (memory expander).

    Are the switches in that case needed to be different (e.g. SW4)?

    We are using Quartus 24.1 to compile the design example but for SW4 off/off/on/off the device is not recognized by Quartus (broken jtag chain) and with SW4 off/off/off/off the device is recognized by Quartus but it is not in user mode but in Error state at the configuration debugger.

    Do you happen to know how we should proceed?

    Best Regards,

    Chloe