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hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output...
Cxl
  • WZ2's avatar
    WZ2
    2 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


xalverti's avatar
xalverti
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello to all,

I am trying to program the same FPGA as a Type3 device (memory expander).

Are the switches in that case needed to be different (e.g. SW4)?

We are using Quartus 24.1 to compile the design example but for SW4 off/off/on/off the device is not recognized by Quartus (broken jtag chain) and with SW4 off/off/off/off the device is recognized by Quartus but it is not in user mode but in Error state at the configuration debugger.

Do you happen to know how we should proceed?

Best Regards,

Chloe