Forum Discussion

hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output...
Cxl
  • WZ2's avatar
    WZ2
    2 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Any update~


  • hxhaa's avatar
    hxhaa
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi，

    Thanks for your help, I succeed to find the 0ddb in my system and run the mlc.

    Best regards

  • hxhaa's avatar
    hxhaa
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi ,

    I notice the cxl example design with 4 slices can't be generated with specific board. I selected none in example design development board, and assigned pin. I refer the .qsf in example in install package download from Intel Agilex® 7 FPGA I-Series Development Kit, and assign pin for dimm channel. But it can't work.

    Considered about no classic example to use, I guess the use of dimm is different from comp. I notice that the example memory design in install package for dimm is x4 x72, and for comp is x8 x72.

    Are there any qsf or design to refer for using more than 2 slice. I need to use all ddr channels on the board.