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hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output...
Cxl
  • WZ2's avatar
    WZ2
    2 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there,

I see, you may refer the wrong user guide. RBES is the new board, sw4 is a JTAG setting for the old board, and you can refer the default switch on page 13 on https://www.intel.com/content/www/us/en/docs/programmable/683288/current/overview.html

Pay attention, on sw8.

And if you still cannot find the device, please go to programmer-> tools-> configuration debugger-> device info and read out the boot stage of device to make sure the device enter into user mode.

Best regards,

WZ


hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago

Hi WZ,

I set sw8 off/off/off/off and sw4 off/off/on/off and enter into user mode. Now the D11 of fpga turns on. Is it means the fpga configuration succussed？

But the system still can't grep 0ddb device, maybe you are right it is caused by the system. I will try it at other system if the fpga work.

Actually, I refer the 763513/763328 document published at 2023.10.11 for quartus 23.3, are there other documents to use? I want to know more about cxl ip and how to use its example design.

Best regards,

hxh