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hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output...
Cxl
  • WZ2's avatar
    WZ2
    3 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

It can be. I'm sorry that my words caused misunderstanding. From my point of view, 4slices cxl controlling 4 particles is what I expect and think is a reasonable application condition.


hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago

Hi，

I implement 2cxlip in top level， but intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_2331/synth/intel_rtile_cxl.sdc said that：

Refclk and avmm clk only will be created when top level port matches QHIP port. Else no refclk and avmm clk will be created. User need to aware of the port name used. This SDC is for user reference for top level clk creation.
I modify this file but after synth it will be reset to the start.
Now there are two refclk0/1/4 for 2 ip, I can't use the same port name as QHIP.Now It can pass the compilation progress and get the sof/pof, and after programmer it did not work. What should I do?