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hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to use CXL IP Design Example on DK-DEV-AGI027RBES

I generate design example in quartus 23.3, choosed type2, AGI027RBES and other config default. The project compiled with timing warnning in Timing Analysis, but the sof file is generated in output...
Cxl
  • WZ2's avatar
    WZ2
    3 years ago

    Hi there,

    Firstly, we should make sure the device enter into the user mode.

    Secondly, could you make sure all the switch like the default setting in the user guide.

    If all this you make sure, I will upload a pof file for you and you can try.

    Of course, it is not ruled out that the problem may be caused by the system.

    Best regards,

    WZ


WZ2's avatar
WZ2
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi there,

Regarding the issue with 4 slices, we are also negotiating with the design team about it. I have run simulations on version 23.3, and the behavior is as expected. However, when it comes to actual board validation, due to some coupling issues with AXI and EMIF and the lack of ideal boards (currently RBES has 2 DDR), the problem has not been resolved smoothly. However, feedback from customers like you can help us continuously improve and expedite the resolution of this issue. I will inform you in the Forum if there are any new developments.

Best regards,

WZ

hxhaa's avatar
hxhaa
Icon for New Contributor rankNew Contributor
2 years ago

Hi,

You say RBES has 2 DDR, do you mean that RBES's dimm can't be used as memory for cxl? Is it possible to implement more than 2 slices on RBES?

Best regards