New ContributorI have a simple system consisting of a TPG and CVO. When I use the NTSC preset the CVO simulates fine. I added a MM BFM and load the CVO configuration registers. The video output of the CVO never starts up. Any suggestions? The BFM is working to configure the TPG.
Regular ContributorHi,
As I understand it, there is no issue when you are simulating with TPG -> CVO. The issue happen when you are using a module to real time configure the CVO. To ensure we are on the same page, just to check with you what is referred by "MM BFM"?
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorBy MM BFM I am referring to the Avalon-MM Master BFM Intel FPGA IP.
My problem seems more basic than I originally thought. I have done quite a bit of simulation of the video path on the previous project using Quartus Std 18.1.
I am now using Quartus Pro 20.2 on an Arria project. I can't get any video out of the Clocked Video Output module using the most basic system (clk, reset, TPG, CVO). I have tried many presets and alignments of ready and reset between the two modules with no success. This is simple stuff compared to my previous project. I'm not sure what has changed and why it does not work. Do you have a simple design like this that you can share with me?
-Steve
Regular ContributorHi Steve,
Thanks for your update. For your information, I have not tested using the MM BFM to perform dynamic reconfiguration. My previous experience when reconfiguring the CVO is directly on the hardware. If you have had the hardware, probably you could give it a try. Another alternative is for your to using your test bench to reconfigure the CVO to isolate out the MM BFM.
Regarding the Q20.2Pro, just to clarify with you is it that when you are simulating simple design with only TPG -> CVO, you are not able to get any output from the CVO?
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi CheePin,
Thank-you for your quick response.
I do not have access to hardware yet..
You asked "Regarding the Q20.2Pro, just to clarify with you is it that when you are simulating simple design with only TPG -> CVO, you are not able to get any output from the CVO?" Yes I am using Q20.2 Pro for the simple design and an Arria. This same simple case does work in Q18.1 Std for a Cyclone V.
Ultimately I want to use 1080p30 connected to the SDI module and load the register configuration using the MM BFM.
-Steve
Regular ContributorHi,
Just to keep you posted on my debug finding. Per my investigation using Q19.4Pro with S10 device (available in my local installation), I found that the issue seems to be happening when we are selecting the embedded sync configuration in the CVO. As I tested with separate wires, the CVO simulation seems to be working fine. I notice that in the Q19.4Pro CVO, there is an additional signal of sdi_cvo_rden. As I tested driving this signal to 1'b1, the CVO has a constant output which seems not right.
Can you try with separate sync to see if it work to narrow down our suspect that it is related to embedded sync?
Thank you.
New ContributorHi,
I also ran the simulation with separate syncs. I observed that the data changed following the input data but I had no sync signals
Regular ContributorHi,
Thanks for your help. For your information, I am currently consulting Factory on this and pending for their response. I will keep you posted on the progress by end of next week or as soon as there is any valid response. Please ping me if you do not hear back from me. For the time being, as a workaround to avoid gating your progress, probably you can look into using Quartus Standard Edition with A10 device.
Sorry for the inconvenience.
Regular ContributorHi,
For your information, I am still pending for valid response from Factory. To avoid further gating your progress, just wonder if you are able to use Standard Edition as a workaround? Sorry for the inconvenience.
New ContributorI have not taken the time to try the standard edition. The Arria 10 requires the Pro edition. I await your solution.
Regular ContributorHi,
Sorry for the delay. I have just received valid responses from Factory on this. As I understand it from Factory, starting Q19.1Pro, the CVO is enhanced to allow direct interfacing with SDI II TX. When you enabled the embedded sync mode, the CVO will have one additional input port of "sdi_cvo_rden". This port is to be connected to the tx_dataout_valid of SDI II TX. You can refer to the VIP user guide -> "Figure 14. Clocked Video Output II with SDI II TX Interface Block Diagram" for further details.
For your information, Factory has also recommended the following reference design which might be helpful for your reference. This design has multi-rate SDI II interfacing with CVI and CVO IPs.
Hopefully this is helpful.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorIt's a nice example in that it includes the CVO and SDI modules however, It does not include a test bench. My initial question was that I get no output from the CVO module in simulation.
Regular ContributorHi,
Yes, you are right, the example is only available for hardware. There is no test bench by the factory. Sorry for the inconvenience.
As a workaround, would you mind to try out in hardware to see if it is working on hardware? You can start with this example design or simplify the design for testing purpose. With a working simple design on hardware, you may create your test bench and simulate it in Modelsim. This could help to narrow down any potential simulation only problem and at the same time serve as workaround to ungate your progress.
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
Just to keep you posted that I have filed a case to Engineering on the CVO no output in simulation with embedded sync mode and currently pending for their response.
Just to check with you if you have had a chance to try on hardware to see if there is any difference in observation?
Thank you very much.
New ContributorI don't have an evaluation card or other hardware to try it on. I am attempting to simulate the design in advance of the board being built.
Regular ContributorHi,
Thanks for your update. For your information, I am still pending for valid response from Factory. As a workaround to avoid further gating your progress, just wonder if you are able to use Quartus version earlier than Q19.1Pro which should be working fine. Please let me know if there is any concern. thank you.
New ContributorHi CheePin,
I can't use earlier versions of Quartus because they are not compatible with the SDI module.
Regular ContributorHi,
Just to keep you posted that Factory is currently looking into this and they mentioned that will update me on the progress by end of the week. I will update you once received any valid response from them.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Regular ContributorHi,
Sorry for the delay. Please correct me if I am wrong, Sherman has helped to open an IPS case on this and I have been keeping Sherman posted on the progress through the IPS case. I believe Sherman have been keeping you posted as well that Engineering is currently debugging into this. To facilitate the tracking, I would suggest we use the IPS case to follow up.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
