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ss's avatar
ss
Icon for New Contributor rankNew Contributor
5 years ago

CVO simulation configuration

I have a simple system consisting of a TPG and CVO. When I use the NTSC preset the CVO simulates fine. I added a MM BFM and load the CVO configuration registers. The video output of the CVO never ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Sorry for the delay. I have just received valid responses from Factory on this. As I understand it from Factory, starting Q19.1Pro, the CVO is enhanced to allow direct interfacing with SDI II TX. When you enabled the embedded sync mode, the CVO will have one additional input port of "sdi_cvo_rden". This port is to be connected to the tx_dataout_valid of SDI II TX. You can refer to the VIP user guide -> "Figure 14. Clocked Video Output II with SDI II TX Interface Block Diagram" for further details.


For your information, Factory has also recommended the following reference design which might be helpful for your reference. This design has multi-rate SDI II interfacing with CVI and CVO IPs.


https://fpgacloud.intel.com/devstore/platform/19.2.0/Pro/intel-arria-10-gx-device-multi-rate-sdi-ii-pass-through-using-video-image-processing-pipeline-reference-design/


Hopefully this is helpful.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin


  • ss's avatar
    ss
    Icon for New Contributor rankNew Contributor
    5 years ago

    It's a nice example in that it includes the CVO and SDI modules however, It does not include a test bench. My initial question was that I get no output from the CVO module in simulation.