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ss's avatar
ss
Icon for New Contributor rankNew Contributor
5 years ago

CVO simulation configuration

I have a simple system consisting of a TPG and CVO. When I use the NTSC preset the CVO simulates fine. I added a MM BFM and load the CVO configuration registers. The video output of the CVO never ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, there is no issue when you are simulating with TPG -> CVO. The issue happen when you are using a module to real time configure the CVO. To ensure we are on the same page, just to check with you what is referred by "MM BFM"?


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin


ss's avatar
ss
Icon for New Contributor rankNew Contributor
5 years ago

By MM BFM I am referring to the Avalon-MM Master BFM Intel FPGA IP.

My problem seems more basic than I originally thought. I have done quite a bit of simulation of the video path on the previous project using Quartus Std 18.1.

I am now using Quartus Pro 20.2 on an Arria project. I can't get any video out of the Clocked Video Output module using the most basic system (clk, reset, TPG, CVO). I have tried many presets and alignments of ready and reset between the two modules with no success. This is simple stuff compared to my previous project. I'm not sure what has changed and why it does not work. Do you have a simple design like this that you can share with me?

-Steve