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senjd's avatar
senjd
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7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down.

Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBUGGING IT. BECAUSE ITS WITH VERY OLDER VERSION (QUARTUS-12.1).

NOT ABLE TO GENERATE THE PROJECT FILES FROM FOLLOWING EXAMPLE.

https://fpgawiki.intel.com/wiki/Design_Example_%E2%80%93_Arria_V_Hard_Memory_Controller_DDR3_SDRAM_UniPHY_533MHz_x32

Dont get why waitrequest goes down.

Any help will highly appreciated.

Thanks in advance

8 Replies

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
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    7 years ago

    ​ Hi senjd,

    The quartus version in wiki is too old. I suggest you to re-generate the example design in newer version.

    There is a known issue on DDR3 SDRAM Controller MegaCore supporting UniPHY.

    Please refer to below KDB solutions on some suggestions which may improve the efficiency of the Avalon interface.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12022011_412.html

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd08142013_467.html

    Hope this helps.

    Thanks

    Regards,

    NAli1

  • senjd's avatar
    senjd
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    7 years ago

    Hi @Nali1,

    Thank you for replying.

    I will try to solve it from given links.

    can we regenerate the example design just to write or read the data into ddr3 controller without qsys?

    because i generated the reference design and i tried to simulate it as per instruction, nothing is happening. there is README.txt file, which clearly says that you just need to run it with do run.do

    But thats simulating the design and adding all the waves the design but signal shows just 0/x/z.

    Let me know your thoughts.

    Thank you

    • senjd's avatar
      senjd
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      7 years ago

      Hi @BCT_Intel,

      Thank you for replying

      I think "abstract PHY" can be available on stratix 10 boards.

      Is there any way to get ddr3 working example design?

      Thank you in advance

  • BoonT_Intel's avatar
    BoonT_Intel
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    7 years ago
    Yes, it is available in S10. You will not see the signal toggling when you turn on this option. Do you mean a working DDR3 example design in S10 development kit? For dev kit, you can use the board test system design to generate the example design and assign location accordingly.
    • senjd's avatar
      senjd
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      7 years ago

      Hi @BCT_Intel

      But i using Arria V GX dev kit with quartus 15.1

      Its not available with this version. How to get reference design for arria v ddr3 controller?

      Thank you in advance.

  • BoonT_Intel's avatar
    BoonT_Intel
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    7 years ago
    ​When you open the DDR3 megawizard GUI, enter all parameter based on the dev kit (you can refer to the board test system design parameters), click finish and a window will pop-up as you either want to generate the example design. Just tick the box and click ok. you will found the example design generate under folder name *_example_design.
  • senjd's avatar
    senjd
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    7 years ago

    Hi @BoonT_Intel​

    Thank you for guidance. so, i generated the design. But its same for simulation also. I connected my module to ddr3 controller at avl interface. but waitrequest is not asserting after one burst.

    Thank You in advance,