Forum Discussion

senjd's avatar
senjd
Icon for New Contributor rankNew Contributor
7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

​ Hi senjd,

The quartus version in wiki is too old. I suggest you to re-generate the example design in newer version.

There is a known issue on DDR3 SDRAM Controller MegaCore supporting UniPHY.

Please refer to below KDB solutions on some suggestions which may improve the efficiency of the Avalon interface.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12022011_412.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd08142013_467.html

Hope this helps.

Thanks

Regards,

NAli1