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senjd's avatar
senjd
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7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Yes, it is available in S10. You will not see the signal toggling when you turn on this option. Do you mean a working DDR3 example design in S10 development kit? For dev kit, you can use the board test system design to generate the example design and assign location accordingly.
  • senjd's avatar
    senjd
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi @BCT_Intel

    But i using Arria V GX dev kit with quartus 15.1

    Its not available with this version. How to get reference design for arria v ddr3 controller?

    Thank you in advance.