Forum Discussion

New Contributor

7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...

BoonT_Intel

Frequent Contributor

7 years ago

Hi Do you turn on "abstract PHY" option for simulation? If you turn on this option, you suppose won't see those DQ/DQs signal toggling. See this for details about abstract phy https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf#page=141

senjd

New Contributor

7 years ago

Hi @BCT_Intel,

Thank you for replying

I think "abstract PHY" can be available on stratix 10 boards.

Is there any way to get ddr3 working example design?

Thank you in advance

Forum Discussion

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

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