Forum Discussion
senjd
New Contributor
New ContributorAfter some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?
I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Do you turn on "abstract PHY" option for simulation? If you turn on this option, you suppose won't see those DQ/DQs signal toggling.
See this for details about abstract phy
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf#page=141
senjdNew Contributor
New ContributorHi @BCT_Intel,
Thank you for replying
I think "abstract PHY" can be available on stratix 10 boards.
Is there any way to get ddr3 working example design?
Thank you in advance
