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senjd
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7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
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    senjd
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    7 years ago

    Hi @BCT_Intel,

    Thank you for replying

    I think "abstract PHY" can be available on stratix 10 boards.

    Is there any way to get ddr3 working example design?

    Thank you in advance