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senjd's avatar
senjd
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7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
senjd's avatar
senjd
Icon for New Contributor rankNew Contributor
7 years ago

Hi @BoonT_Intel​

Thank you for guidance. so, i generated the design. But its same for simulation also. I connected my module to ddr3 controller at avl interface. but waitrequest is not asserting after one burst.

Thank You in advance,