After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

Hi @Nali1,

Thank you for replying.

I will try to solve it from given links.

can we regenerate the example design just to write or read the data into ddr3 controller without qsys?

because i generated the reference design and i tried to simulate it as per instruction, nothing is happening. there is README.txt file, which clearly says that you just need to run it with do run.do

But thats simulating the design and adding all the waves the design but signal shows just 0/x/z.

Let me know your thoughts.

Thank you