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senjd's avatar
senjd
Icon for New Contributor rankNew Contributor
7 years ago

After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx?

I am trying to do transaction DDR3 transactions. Some of the transaction is happening properly, but after that waitrequest goes down. Unfortunately, NOT ABLE TO ACCESS ALTERA EXAMPLE DESIGN FOR DEBU...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
​When you open the DDR3 megawizard GUI, enter all parameter based on the dev kit (you can refer to the board test system design parameters), click finish and a window will pop-up as you either want to generate the example design. Just tick the box and click ok. you will found the example design generate under folder name *_example_design.