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Altera_Forum's avatar
Altera_Forum
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14 years ago

vht test bench examples

Hello,

I am specifying altera to generate a .vht test bench for my vhdl project. I want to modify this test bench so that I can specify the input signals to be some value at different times instead of the current undefined (U).

SIGNAL clk : STD_LOGIC;

.

.

clk : IN STD_LOGIC;

.

.

.

clk => clk,

.

-- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

clk <='1'; wait for 10 ns;

clk <='0'; wait for 10 ns;

-- code executes for every event on sensitivity list

--WAIT;

I have been trying to find for hours some example modified test bench files that I can work off. The above code does not change the clock signal in the signal viewer in modelsim-altera at all.

thank you

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    The above code does not change the clock signal in the signal viewer in modelsim-altera at all.

    --- Quote End ---

    Because you have told the process to wait (stop) after toggling the signal once. For a clock, what you want is 

    
process
begin
   clk <= '0';
   wait for 10 ns;
   clk <= '1';
   wait for 10 ns;
end process;
    and the process will repeat in an infinite loop repeating these waits, and hence generate a clock.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sorry, the wait signal in my code is commented out. I copied your code exactly as you specified in the section the vht generated test bench says to put code you want to run indefinetly. However it is still not showing up on my signal viewer.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    However it is still not showing up on my signal viewer.

    --- Quote End ---

    How are you adding the signal to the viewer? You have to drag it from the signals list into the viewer.

    Assuming you're new to Modelsim, do the following ...

    In Modelsim, display the signals and wave window

    view signals wave

    then add all top-level signals

    add wave *

    then delete the ones you do not want to see, and select levels of the hierarchy to view the signals at that level of the design, and drag them across to the wave window. Right click and add dividers where you want to name blocks of signals, and then save it as a 'wave.do' file, or name of your choice, then later you can just type 'vsim mytest; do wave.do' to populate the wave window.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for the help

    In Quartus I made a vht test bench file. When I compile quartus I tell it to run the test bench in modelsim. When modelsim loads it lists all the signals in the Objects window and loads the wave window. All my input signals are being shown as undefined, however it does show signals being propagated internally within my system (which is to be expected, not everything in my system is dependent on an input signal).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    In Quartus I made a vht test bench file. When I compile quartus I tell it to run the test bench in modelsim.

    --- Quote End ---

    I run Modelsim independently of Quartus, so I don't know exactly what is going on. However, here's what should be happening.

    If Quartus is creating an entity called test_bench, and inside that entity is where you have your clocks and input stimulus, then in Modelsim you can do the following; 

    #  Stop the current simulation
quit -sim
#  Simulate the test_bench design
vsim test_bench
#  Run the simulation for 10 microseconds
run 10 us
#  I've made some edits, now I want to re-run# #  First rebuild the VHDL files that I've edited
vcom test_bench.vhd# #  Force the design changes to be loaded
restart -f# #  Run the design to see if my edits worked ...
run 10 us
    Try that.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When I follow your instructions I get the error, "#No Design Loaded!"

    I am creating the test bench (vht file) by in Quartus:

    Processing -> Start -> start test bench writer

    The first couple lines in the file that is generated is:

    "-- ***************************************************************************

    -- This file contains a Vhdl test bench template that is freely editable to

    -- suit user's needs .Comments are provided in each section to help the user

    -- fill out necessary details.

    -- ***************************************************************************

    -- Generated on "07/06/2011 10:00:43"

    -- Vhdl Test Bench template for design :"
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    When I follow your instructions I get the error, "#No Design Loaded!"

    --- Quote End ---

    What happened when you typed 'vsim test_bench' (change the name to whatever your testbench is named of course)?

    That should load the design.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    When I typed :

    vsim Test_bench.vht

    Result:

    # OpenFile Test_bench.vht

    The error is when I type "run 10 us"
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    When I typed :

    vsim Test_bench.vht

    Result:# OpenFile Test_bench.vht

    --- Quote End ---

    That is not the correct command. You need to drop the .vht.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you,

    Okay it simulates now and I can drag signals over to the wave window. However, I still have undefined for the clock even with your specified code for the clock in the test bench.