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In Quartus I made a vht test bench file. When I compile quartus I tell it to run the test bench in modelsim.
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I run Modelsim independently of Quartus, so I don't know exactly what is going on. However, here's what should be happening.
If Quartus is creating an entity called test_bench, and inside that entity is where you have your clocks and input stimulus, then in Modelsim you can do the following;
# Stop the current simulation
quit -sim
# Simulate the test_bench design
vsim test_bench
# Run the simulation for 10 microseconds
run 10 us
# I've made some edits, now I want to re-run# # First rebuild the VHDL files that I've edited
vcom test_bench.vhd# # Force the design changes to be loaded
restart -f# # Run the design to see if my edits worked ...
run 10 us
Try that.
Cheers,
Dave
Honored Contributor
