Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorvht test bench examples
Hello, I am specifying altera to generate a .vht test bench for my vhdl project. I want to modify this test bench so that I can specify the input signals to be some value at different times ins...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In Quartus I made a vht test bench file. When I compile quartus I tell it to run the test bench in modelsim. --- Quote End --- I run Modelsim independently of Quartus, so I don't know exactly what is going on. However, here's what should be happening. If Quartus is creating an entity called test_bench, and inside that entity is where you have your clocks and input stimulus, then in Modelsim you can do the following;
# Stop the current simulation
quit -sim
# Simulate the test_bench design
vsim test_bench
# Run the simulation for 10 microseconds
run 10 us
# I've made some edits, now I want to re-run# # First rebuild the VHDL files that I've edited
vcom test_bench.vhd# # Force the design changes to be loaded
restart -f# # Run the design to see if my edits worked ...
run 10 us
