vht test bench examples

Hello,

I am specifying altera to generate a .vht test bench for my vhdl project. I want to modify this test bench so that I can specify the input signals to be some value at different times instead of the current undefined (U).

SIGNAL clk : STD_LOGIC;

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clk : IN STD_LOGIC;

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clk => clk,

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-- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

clk <='1'; wait for 10 ns;

clk <='0'; wait for 10 ns;

-- code executes for every event on sensitivity list

--WAIT;

I have been trying to find for hours some example modified test bench files that I can work off. The above code does not change the clock signal in the signal viewer in modelsim-altera at all.

thank you