Honored ContributorHello, maybe a dummy question:
I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->b"011" + b"010" = b"0110" -3-3=-6 ----->b"101" + b"101" = b"1010" A,B:std_logic_vector(2:0); result:std_logic_vector(3:0); but if I do this assignation result<=A+B; quartus said me "expression has 3 elements, but must have 4 elements" Thank you.
Honored Contributorresult <= sign_extend(A) + sign_extend(B);
or result <= (A(2) & A) + (B(2) & B);Honored ContributorHello
I was doing the addition between two 22 bits std_logic_vector. And I had to store the result in a 29 bits std_logic_vector, So I was doing this data_1_2005_29bits <= (data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(21) & data_1_2005(20 downto 0) ); I was repeating the sign 6 times, but with the function sign_extend my code will be more legible. Thank you. DABGHonored ContributorHello,
I have one more question, the function "sign_extend" is also valid with the arith package? I have this error after compiling: Error (10482): VHDL error at sum_data.vhd(76): object "sign_extend" is used but not declared Thank youHonored ContributorIf you mean STD_LOGIC_ARITH library, it has a SXT() function, if I remember right. It's actually sufficient to extend one of two summands to the result size.
Honored ContributorHello FVM,
Yes, I mean std_logic_arith, sorry. Well I extend 7 times the sign because the result will be the addition between multiples inputs. result<=A+B+c+...; Well, maybe I will begin with the package numeric_std, to see the advantages. Thank you. dabgHonored ContributorIn numeric_std, you use the resize() function for the same result. This works for signed and unsigned types.
Honored ContributorYes, I meant resize() instead of sign_extend() in my first post. It works great and the code is still readable, typicaly you only need to extend one of the operands.
Honored ContributorI had faced to this subtle of IEEE.numeric_std addition in VHDL.
So as to do the true addition (= addition with carry) I have to extend (resize) one operand, as you said to the desired size (max size + number of '+'). 16 bits + 16 bits => 17 bits 16 bits + 16 bits + 16 bits=> 18 bits result <= resize(s1_16bits + s2_16bits , 17); doesn't do what expected : the carry will be forgotten and result(17) always '0' (for unsgined) 7 years, this "bug" is present in my project. Why IEEE did not pay attention to that ?Honored Contributorresult <= resize(s1_16bits , 17) + s2_16bits;
