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Altera_Forum
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16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello

I was doing the addition between two 22 bits std_logic_vector.

And I had to store the result in a 29 bits std_logic_vector,

So I was doing this

data_1_2005_29bits <=

(data_1_2005(21) & data_1_2005(21) & data_1_2005(21) &

data_1_2005(21) & data_1_2005(21) & data_1_2005(21) &

data_1_2005(21) & data_1_2005(21) &

data_1_2005(20 downto 0) );

I was repeating the sign 6 times, but with the function sign_extend my code will be more legible.

Thank you.

DABG