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Altera_Forum
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16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello FVM,

Yes, I mean std_logic_arith, sorry.

Well I extend 7 times the sign because the result will be the addition between multiples inputs.

result<=A+B+c+...;

Well, maybe I will begin with the package numeric_std, to see the advantages.

Thank you.

dabg