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Altera_Forum
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16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
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Altera_Forum
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12 years ago

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result <= resize(s1_16bits + s2_16bits , 17); doesn't do what expected : the carry will be forgotten and result(17) always '0' (for unsgined)

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Essentially a wrong expectation. The 16 bit numbers are added first, with 16 bit result size according to VHDL rules, unfortunately involving a possible overflow. Then sign extended after the overflow occurred. For the expected result, you need to sign extend first, then add. 

result <= resize(s1_16bits , 17) + s2_16bits;