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Altera_Forum
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16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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7 years, this "bug" is present in my project.

Why IEEE did not pay attention to that ?

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Its not a bug, you just wrote the code wrong, as FvM explained.

The new fixed point libraries do width extension automatically.