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Altera_Forum
Honored Contributor
Honored Contributorvhdl addition result size
Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
Altera_ForumHonored Contributor
Honored ContributorYes, I meant resize() instead of sign_extend() in my first post. It works great and the code is still readable, typicaly you only need to extend one of the operands.
