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Altera_Forum
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16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

result <= sign_extend(A) + sign_extend(B);

or

result <= (A(2) & A) + (B(2) & B);