Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

vhdl addition result size

Hello, maybe a dummy question: I am using arith package. If I need to add 2 signed std_logic_vector of 3 bits, The output should be a std_logic_vector of 4 bits, 3+3=6 ----->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I had faced to this subtle of IEEE.numeric_std addition in VHDL.

So as to do the true addition (= addition with carry) I have to extend (resize) one operand, as you said to the desired size (max size + number of '+').

16 bits + 16 bits => 17 bits

16 bits + 16 bits + 16 bits=> 18 bits

result <= resize(s1_16bits + s2_16bits , 17); doesn't do what expected : the carry will be forgotten and result(17) always '0' (for unsgined)

7 years, this "bug" is present in my project.

Why IEEE did not pay attention to that ?