Synthesizable delay with VHDL (One single output pulses)

Thanks in advance for your nice instructions.

What I am doing is producing a single output pulse. It is a simple output but due my little knowledge it becomes complicated for me.

What I want in output is like this [SUB]--------0-------[/SUB][SUP]-------1-------[/SUP][SUB]---------0-------[/SUB]

It is simple but there are some points, As the pulse width (When pulse is "1") is important for my experiment, I have used counters to count clock cycles and make output "1" for a certain clock cycles make output "0" after certain clock cycles.

But the problem is at the starting point. When I connect it to Oscilloscope the output is "1" before my commands.

I have attached the Oscilloscope waveform. The waveform is always "1" before my real command. I want 0 and 1 and then 0 again without any other repetition.

Please look at the code and help me for correction.

As I write in the code, After 2 clock pulse (Constant a) output become "1" and after 3 clock pulse (Constant b) output become "0" again, This is for controlling the output pulse width. But the problem is about before starting. As you see in the attachment picture, output of FPGA already is "1" and then my codes acts.

I am sure there are some mistake in the code, please help me to correct it.

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;
entity ltd_auto is
port    (        clk : in std_logic;
        data_out: out std_logic    );
end ltd_auto;
Architecture behavioral of ltd_auto is
signal         c : integer:= 0;
constant     a : integer:= 2;
constant        b : integer:= 3;
type state_type is (idle, delay, zero);
signal  next_s: state_type;
begin
     process (clk)
        begin            if (rising_edge(clk))then
                case next_s is
                    when idle =>
                        c <= c + 1;
                        next_s <= delay; 
                   when delay =>
                        if (c = a) then
                            data_out <= '1';
                        end if;
                        if (c = b) then
                        data_out <= '0';
                        next_s <= zero;
                        else
                        c <= c + 1;
                        end if;
                    when zero => 
                   c <= 0;
                end case;
            end if;
    end process;
end behavioral;

another code that i wrote with the same problem

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ltd_1 is
port    (        clk : in std_logic; 
       data_out: out std_logic    );
end ltd_1;
Architecture behavioral of ltd_1 is
signal         c : integer:= 0;
constant     a : integer:= 1;
constant        b : integer:= 2;
begin 
    process (clk) 
       begin  
          if (falling_edge(clk))then 
               c <= c + 1;
                    if (c = a) then 
                   data_out <= '1';
                    elsif (c = b) then
                    data_out <= '0';
                    end if;
            end if;
    end process;
end behavioral; 
               

Thank you in Advance for your help.