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Altera_Forum
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12 years ago

Synthesizable delay with VHDL (One single output pulses)

Thanks in advance for your nice instructions. What I am doing is producing a single output pulse. It is a simple output but due my little knowledge it becomes complicated for me. What I want in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You get repeated pulses because you set the state machine back to the IDLE state after the delay state, and hence it loops forever.