TSE MAC+PCS (SGMII, Cyclone 10 GX): mdio_out/mdio_oen never toggle, no matter what I write

Cyclone 10 GX (10CX220Y), Triple-Speed Ethernet IP: core_variation=MAC_PCS, transceiver_type=NONE (external LVDS SERDES, TBI), enable_sgmii=true, enable_use_internal_fifo=true, useMDIO=true.

Trying to read/write an external Marvell 88E1111 over MDIO via the MAC's control_port (System Console + JTAG-to-Avalon).

Verified working: basic CSR read/write (rev, scratch_pad), tse_rst=0 / xcvr_ready=1 (out of reset), mdc toggling correctly at 1.25MHz on the pin, MDIO_ADDR0 (0x0F) and MDIO_ADDR1 (0x10) are real R/W registers (write/readback matches), mdio_oen tri-state glue matches Intel's own reference template exactly.

Not working: I added (* preserve *) to mdio_in/mdio_out/mdio_oen and tapped them directly with SignalTap on TSEIP's own ports. With a falling-edge trigger on mdio_out, and while repeatedly writing MDIO_ADDR0/MDIO_ADDR1 and reading/writing both the phy0 (0x40+n) and phy1 (0x60+n) windows with genuinely varying values — mdio_out never shows a single transition. Since even a bare MDIO read frame must produce at least one falling edge (end of the all-1s preamble), this looks like no real MDIO transaction is ever being started from the CSR side.

What am I missing — is there another enable/start bit or busy/status flag needed to actually kick off an MDIO transaction on this core_variation/config? Any pointer to the MDIO register section for this exact IP version (Quartus Prime Pro 24.1) would help too.