Forum Discussion
Occasional Contributor8 port 10/25G ethernet interface in Stratix 10
We have custom board made with Stratix 10 1ST085EN2F43I2LG. The board has 8 SFP28 ports the needs to talk to 10/25G ethernet devices. This board is used to test the connected devices by sending a fixed Ethernet packets and analyse the received Ethernet packets.
The SFP ports needs to be selectable between 10G and 25G and enable/Disable RS-FEC. Also need the MAC statistics registers and PTP timestamping.
We could see two different IP cores available for this in the IP catalogue,
- 25G Ethernet Stratix 10 IP, and
- Ethernet Stratix 10 E-Tile Hard IP.
Which one is the right IP for this requirement.
9 Replies
Sajeev_antonynot able to attach archived project or fitter report file
paveetirrasrie_AlteraFrequent Contributor
Hello Sanjeev,
We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.
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Best regards,
Altera Technical Support
- Sajeev_antony
o_tx_serial_n Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments on output pin 1
i_rx_serial_n Missing I/O standard 2
- Sajeev_antony
The ip generates seperat P and N signals of the serial TX and RX lanes as,
o_tx_serial, o_tx_serial_n, i_rx_serial, i_rx_serial_n
I gave pin location assignments to these pins.
But Quartus 2026.1 says
Critical Warning(25196): A programming file will not be generated because the assembler identified user pins missing pin location assignments. Refer to the I/O Assignment Warnings table in the fitter report for a list of unassigned pins. You can assign these pins in the Pin Planner tool and recompile to allow programming file generation to pass.
In the fitter list it lists o_tx_serial_n and i_rx_serial_n
How to give pin assignment to these dedicates transiver lines.
- paveetirrasrie_Altera
Hello,
Can you try to just assign o_tx_serial and i_rx_serial and run the compilation, let the Quartus to auto assign the N signals.
Kindly do let me know if that works.
Regards,
Pavee
- Sajeev_antony
Is there any simple design that i can use to test the ports.
Just want to send a fixed ethernet packet from one port and receive the same at another port and check the received data.
I have set the reference clock to 156.25MHz.
Also what is the procedure to switch between 10G and 25G rates.
- paveetirrasrie_Altera
Testing with a Fixed Ethernet Packet (Port-to-Port / Loopback)
The quickest path is the E-Tile Hard IP for Ethernet hardware design example, which includes a built-in packet generator and checker. The hardware design example includes the E-Tile Hard IP for Ethernet IP core plus a PCS packet generator and checker that coordinates IP core programming, packet generation, and packet verification. 100GE PCS with Optional RS-FEC Hardware Design Example Components
After compiling and programming the device via JTAG, you drive it through the Quartus Prime System Console using a Tcl script. The key commands you'll use are:
start_pkt_gen — starts the packet generator; stop_pkt_gen — stops it. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example
chkphy_status — displays clock frequencies and PHY lock status; chkmac_stats — displays MAC statistics counter values; clear_all_stats — clears the statistics counters. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example
loop_on — turns on internal serial loopback; loop_off — turns it off. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example
To configure the packet generator for a fixed-size packet, use these registers:
0x1008 (Packet Size Configure) — bits [10:0] specify the transmit packet size in bytes. 10GE/25GE Design Examples Registers
0x1009 (Packet Number Control) — specifies the number of packets to transmit from the packet generator (HW reset value = 0xA). E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration
0x1010 (PKT_GEN_TX_CTRL) — bit [1] is the packet generator disable bit (write 1 to turn off, 0 to turn on); bits [5:4] = 01 selects fixed mode; bit [6] = 1 enables using register 0x1009 to stop the generator after a fixed packet count. E-Tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration
Switching Between 10G and 25G Rates (Dynamic Reconfiguration)
The 10G/25G Ethernet Dynamic Reconfiguration design example demonstrates a dynamic reconfiguration solution for Stratix 10 devices using the E-Tile Hard IP for Ethernet IP core, supporting variants including 25GE with RS-FEC and PTP, 25GE, 10GE, and 1GE. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
The high-level procedure for each rate switch transition is:
Assert (toggle) the sl_tx_rst_n and sl_rx_rst_n reset signals. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Disable SERDES using PMA attribute code 0x0001. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Trigger PMA analog reset. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Change the transceiver TX bit/refclk ratio to the destination rate (refclk = 156.25 MHz), then change the transceiver RX bit/refclk ratio to the destination rate (refclk = 156.25 MHz). 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Reconfigure the registers for the Ethernet, RS-FEC, and transceiver blocks — the details of the changed register values are in the c3_reconfig.c file generated with the design example. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Adjust the phase offset of the recovered clock using PMA attribute code 0x000E. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Re-enable SERDES using PMA attribute code 0x0001. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
Deassert sl_tx_rst_n and sl_rx_rst_n, then for 10G/25G DR transitions wait for PIO_OUT[4:0] = 0x1F (o_sl_tx_ptp_ready, o_sl_rx_pcs_ready, o_tx_pll_locked, o_sl_tx_lanes_stable, o_sl_rx_ready, o_sl_ehip_ready all asserted). 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
- paveetirrasrie_Altera
Good day.
Just wanted to check with you, is your concern has been addressed?
Feel free to let me know if you have further query. Happy to help.Regards,
Pavee - paveetirrasrie_Altera
Hello,
Your part number is 1ST085EN2F43I2LG. This is a Stratix 10 E-tile device (TX variant).
The 25G Ethernet Intel FPGA IP supports Stratix 10 L- and H-tile devices only. Stratix 10 devices with both E- and H-tile transceivers are supported, but the IP core can only utilize the H-tile transceiver. Since your device is an E-tile TX part, this soft IP is not the right choice.
The E-Tile Hard IP for Ethernet is the correct IP for your board. It is the hard IP designed for your E-tile device, natively supports 10G/25G dynamic reconfiguration, RS-FEC (on 25G), MAC statistics counters, PTP timestamping, and packet generation/checking, all the features your test board requires.
Regards,
Pavee
