8 port 10/25G ethernet interface in Stratix 10

The ip generates seperat P and N signals of the serial TX and RX lanes as,

o_tx_serial,  o_tx_serial_n, i_rx_serial,  i_rx_serial_n

I gave pin location assignments to these pins.

But Quartus 2026.1 says

Critical Warning(25196): A programming file will not be generated because the assembler identified user pins missing pin location assignments. Refer to the I/O Assignment Warnings table in the fitter report for a list of unassigned pins. You can assign these pins in the Pin Planner tool and recompile to allow programming file generation to pass.

In the fitter list it lists o_tx_serial_n and i_rx_serial_n

How to give pin assignment to these dedicates transiver lines.