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Altera_Forum
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12 years ago

Synthesizable delay with VHDL (One single output pulses)

Thanks in advance for your nice instructions. What I am doing is producing a single output pulse. It is a simple output but due my little knowledge it becomes complicated for me. What I want in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Tricky: Thanks for the reply.

I have mentioned this state machine makes a loop. (Idle to delay to idle to delay etc). As I said I want to cancel the loop. Any idea how to cancel the loop for only one output pulse with width controbillity? I tried to describe another state with name of "zaro" to make the counter c <=0 but it won't help.

This is what I mean [SUB]----0----[/SUB][SUP]--------1-------[/SUP][SUB]------------------0------------------[/SUB]