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Altera_Forum
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12 years ago

Synthesizable delay with VHDL (One single output pulses)

Thanks in advance for your nice instructions. What I am doing is producing a single output pulse. It is a simple output but due my little knowledge it becomes complicated for me. What I want in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

one more to mention is, that the FPGA Output Pins are tri-state as long as the FPGA has not configured. Thus in case you do not pull the Signal down by an external resistor, there will always be a high Signal till the FPGA has configured and started to execute programming...