Synthesizable delay with VHDL (One single output pulses)

Another point, In the below mentioned code I have a pulse like this [SUB]----0---[/SUB][SUB]----0---[/SUB][SUB]---0----[/SUB][SUP]-----1----[/SUP][SUB]----0---[/SUB][SUB]----0---[/SUB][SUB]---0----[/SUB][SUP]-----1----[/SUP]. The point is that I need only the first "1", I do not need any pulses any more. But as I have to control the pulse width of my signal (When the output is "1") therefore I need to use counter.

I have used the type command and two state (idle and delay). After idle state it goes to delay state and if it was (c=a) output become 1 and if it was (c=b) output become 0 (Because I need to control the pulse width). After it becomes 0 it goes again to delay state. I have tried many other options to don't let goes to idle after delay state. What is your suggestion for rejection of repetition.

I mean, only one pulse in output with width controllability??

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity delay_auto is

port

(

clk : in std_logic;

data_out: out std_logic

);

end delay_auto;

Architecture behavioral of delay_auto is

signal c : integer:= 0;

constant a : integer:= 5;

constant b : integer:= 6;

type state_type is (idle, delay);

signal next_s: state_type;

begin

process (clk)

begin

if (rising_edge(clk))then

case next_s is

when idle =>

c <= c + 1;

next_s <= delay;

when delay =>

if (c = a) then

data_out <= '1';

end if;

if (c = b) then

data_out <= '0';

next_s <= idle;

c <= 0;

else

c <= c + 1;

end if;

end case;

end if;

end process;

end behavioral;