Synthesizable delay with VHDL (One single output pulses)

I might have not got the clue on your Intention, but in case you just Need one pulse when the FPGA goes online, this should be possible by just implementing a Counter that starts couting with every rising edge of clk as Long as the final value is not reached. the Output can be set high for countervalue being higher than x (this is the number of clocks delaying the high pulse) and being lower than y (with y-x defining the pulse width):

signal Counter : integer range 0 to 1023;

signal start_delay : integer range 0 to 1023;

signal pulse_width: integer range 0 to 1023;

process(clk,POR)

begin

if (POR='1') then

Counter <= 0;

Output <= '0';

elsif rising_edge(clk) then

if (Counter < 1023)

then

Counter <= Counter+1;

end if;

if (Counter < start_delay)

then

Output <= '0';

elsif (Counter < (start_delay+pulse_width))

then

Output <= '1';

else

Output <= '0';

end if;

end if;

end process;

The POR signal is a internally generated (or external applied) PowerOnReset signal - not functionally necessary...

I just wrote this here - did not check for Syntax in QII yet, thus excuse any typo...